This invention relates to a current mirror circuit suitable for a low voltage integrated circuit.
A current mirror circuit is usually used as an active load of a differential amplifier, and various types of current mirror circuits are known. FIGS. 1(a) to 1(c) show examples of such known current mirror circuits.
FIG. 1(a) shows a known current mirror circuit which has transistors Qa1 and Qa2 with their respective base-emitter paths connected in parallel. This circuit arrangement has a drawback in that an error of a comparatively large magnitude is provided between an input current Iin and an output current Iout due to the base current of transistors Qa1 and Qa2 as is well known in the art.
FIG. 1(b) is an improved current mirror circuit which comprises a compensating transistor Qb3 of the same conductivity type to transistors Qb1 and Qb2. The transistor Qb3 has its emitter connected to the bases of transistors Qb1 and Qb2, its base connected to the collector of transistor Qb1 and its collector connected to circuit ground. According to this circuit arrangement, the effect of the base current of transistors Qb1 and Qb2 on the input current Iin can be reduced by a factor of the current amplification factor of transistor Qb3. In this circuit, however, a supply voltage at the input terminal supplied with the input current Iin must be lower than Vcc by the sum of the base-emitter voltages (about 0.7 volt in case of a silicon transistor) of transistors Qb1 and Qb3. This involves a disadvantage that a relatively high supply voltage, which is about 1.4 volts or above, is necessary for operating the circuit.
FIG. 1(c) shows still another improved current mirror circuit. This circuit comprises emitter-coupled NPN transistors Qc3 and Qc4 in addition to current mirror PNP transistors Qc1 and Qc2. Transistor Qc3 has its collector connected to a supply voltage Vcc and its base connected to the collector of transistor Qc1. On the other hand, transistor Qc4 has its collector connected to the bases of transistors Qc1 and Qc2 and its base connected to a reference voltage Vref. The emitters of transistors Qc3 and Qc4 are connected through a current source of current value IO to circuit ground. The current IO is set to be higher than the sum of the base currents of transistors Qc1 and Qc2.
With this circuit the error between the input current Iin and the output current Iout is IO/.beta.3 at maximum (.beta.3 is the current amplification factor of transistor Qc3). It will be understood that, since IO is relatively low, the error is small. Transistor Qc3 is provided for the level shift, and thus the supply voltage at the input terminal is determined by Vref. Namely, the circuit of FIG. 1(c) can be operated from a low supply voltage so long as Vref has such a magnitude to render all the transistors conductive. However, this circuit arrangement is complicated in construction in that the generation of the reference voltage Vref applied to the base of transistor Qc4 is required.